Various embodiments of this disclosure relate to compile-time schedulers and, more particularly, to compile-time schedulers with load-store queue awareness.
In executing a program, a processor core may need to perform an ordered sequence of arithmetic instructions and memory access instructions. Generally, performing a memory access instruction can take two or more orders of magnitude more time than an arithmetic operation. The specific order of this sequence may be determined by a compiler that converted the program into code executable by the processor.
A load-store queue (LSQ) is a shared queue used by one or more processor cores of a computer processor, where each core inserts memory access instructions into the LSQ during execution of a program. Generally, the LSQ is a first-in-first-out (FIFO) queue, such that memory access instructions are handled in the order they are received at the LSQ. When a memory access instruction is handled, the desired memory addresses are accessed and the retrieved data is returned to the requesting processor core.
The LSQ has a finite capacity and thus has the potential to become full. When the LSQ is full, subsequent memory access instructions from a processor core are forced to stall. In the case of an in-order core, even arithmetic operations that are memory-independent and otherwise ready to execute will stall if they are scheduled for execution after the memory access instruction causing the stall.